I2C Core with Avalon Bus Interface

I2S Core with Avalon Bus Interface

USB Connect 1.1

USB Connect 1.1 standard was introduced to connect peripheral devices to a PC. Its main advantage is the convenience of a ‘plug-and-play’ environment. All devices are automatically configured at connection to any free port. Experience First USB Connect 1.1 performs all USB functions for a peripheral device in a customer-specific ASIC. It can be configured to different customer applications. For a high level of flexibility, the application microcontroller runs all configurable protocol functions. If the application cannot handle the protocol functions, the USB controller available with the Plus option can handle this tasks. The synthesizable Verilog code can be mapped to a technology of the customers choice. The USB is prepared for insertion of a scan path using ATPG.

Utopia Level 3 Slave

Utopia Level 3 Slave is a flexible parameterized core for ATM networks with 8,16, or 32 bit bus widths and can operate at clock speeds above 40 MHz, and up to 104 MHz. It has many optional features such as single or multi-CLAV operation parity, checking on transmit port (Tx_Slave), and variable cell lengths.

Utopia Level 3 Master

Utopia Level 3 Master is a flexible parameterized core with 8, 16, or 32 bit UTOPIA bus widths and local bus widths, and can operate at speeds up to 50 MHz. The UTOPIA Master or ATM device consists of a transmitter and a receiver which interface to a slave (PHY) interface and an ATM local bus interface. It has many optional features such as parity checking (receive direction), parity generation (transmit direction), variable cell lengths, octet (in SPHY mode only) or cell level handshaking.


10/ 100 Mbps Media Access Controller (The MAC 10/100 Core implements the IEEE 802.3) The MAC 10/100 Core interface with the Physical layer chip on the network side, and to the system interface and the MAC support logic on the other side. It can be used in 10/100 Mbps Ethernet solutions like network adapter cards, network switches, bridges and any Ethernet network-based solutions. The MAC 10/100 Core can interface with a PHY device across the MII or use the functionality to interface with a PHY device across the symbol interface or serial interface.